This invention relates generally to integrated circuit delay elements. More particularly, the invention relates to a system, circuit and method for low voltage operable, small footprint delay.
Synchronous integrated circuits rely on precise timing to operate properly. Frequently, there is a need to delay one or more signals to compensate for delays along other signal paths in an integrated circuit. Delay circuits are well known to one of ordinary skill in the art. Perhaps the simplest conventional delay circuit consists of a resistor and capacitor in series (RC network). The RC network consists of an input at one end of the resistor and the output at the other end of the resistor. The capacitor has one node connected to the output and the other node connected to ground potential. At steady state, a low voltage on the input results in a low voltage across the capacitor and at the output. If the input abruptly changes from low to high, the output remains low initially as the capacitor charges up and the voltage on the output rises to a high. Eventually the output will be at a high voltage matching the input voltage. Conversely, as the input voltage abruptly changes to a low voltage, the capacitor initially holds the output at a high. As the capacitor discharges through the resistor, the voltage across the capacitor, output, begins to drop and eventually matches the low voltage on the input. In this way the inherent delay of the RC network is used to delay an input signal at the corresponding output.
FIG. 1 illustrates a conventional delay circuit 100 suitable for use with digital integrated circuits that incorporates an RC network. The terms xe2x80x9ctiedxe2x80x9d, xe2x80x9ccoupledxe2x80x9d and xe2x80x9cconnectedxe2x80x9d are used synonymously herein. Delay circuit 100 includes a p-channel metal oxide semiconductor (PMOS) transistor P1 with a source tied to power, VDD, and a gate tied to ground, GND. Delay circuit 100 further includes a PMOS transistor P2 with a source node tied to a drain node of PMOS transistor P1 and a drain node tied to a first end of resistor R. Delay circuit 100 further includes an n-channel metal oxide semiconductor (NMOS) transistor N1 with a drain node connected to the first end of resistor R and a gate node connected to input signal, IN, and a gate node of PMOS transistor P2. Delay circuit 100 further includes an NMOS transistor N2 having a drain node connected to the source node of NMOS transistor N1, a gate node coupled to VDD and a source node tied to ground potential, GND. Delay circuit 100 further includes a capacitor C1 with one end tied to signal A and the other end tied to resistor R. Delay circuit 100 further includes an inverter 102 with input connected to signal A and an output driving output signal B.
FIG. 2 illustrates a timing diagram showing input signal IN relative to signal A and output signal B for the conventional delay circuit 100 shown in FIG. 1. As shown in FIG. 2, delay circuit 100 achieves a delay, td1, for a rising edge in the input signal IN to appear on output signal B. However, there is a significant internal delay, xcex94t1, in fully discharging (or charging) capacitor C1 as illustrated by signal A in FIG. 2. This internal delay limits the switching speed of conventional delay circuit 100 because the internal delay must expire before the next transition on input signal IN. Otherwise, the duration of delay generated by the delay circuit 100 may be unpredictable if signal A starts from some voltage other than a rail voltage, i.e., VDD or GND. Thus, for high frequency applications, it is desirable for the internal node of a delay circuit to quickly return to a rail voltage after the delayed output signal is achieved. Additionally, such a conventional delay network 100 is typically placed many times on a typical IC. Since the time delay is dependant on the values of the resistor R1 and capacitor C1 and the resistor and capacitor elements are relatively large, long delay times can be costly in terms of IC area or xe2x80x9creal estate.xe2x80x9d
Thus, there exists a need in the art for a system, circuit and method for low voltage operable, small footprint delay that achieves signal delays useful for high-speed applications requiring less IC real estate than conventional delay circuits.
The present invention includes a system, circuit and method for low voltage operable, small footprint delay. Delay circuits according to the present invention may include input switching and output switching devices separated by an RC network. The input switching devices may be coupled to limiting devices. Furthermore, bypass devices may be coupled to the limiting devices to rapidly pre-condition internal signals of the delay circuit. Pre-conditioning internal signals enables higher frequency operation of the delay circuits of the present invention relative to conventional delay circuits. Additional features of the delay circuits of the present invention include programmable resistance networks and programmable capacitance networks allowing precise control of the delay generated by the RC network formed by same.
These embodiments of the present invention will be readily understood by reading the following detailed description in conjunction with the accompanying figures of the drawings.